1. Field of the Invention
The present invention relates to a processor apparatus and a computer system equipped with such a processor apparatus, and more particularly relates to a technique to improve instruction utilization of an instruction in a single operation processing mode, in which a coprocessor is not run in parallel in a parallel processor including a plurality of processors and thereby being capable of processing a plurality of operations in one clock cycle.
2. Background Art
Conventionally, a multiple parallel processor which carries out a plurality of operation instructions in one clock cycle has been put into practical use. FIG. 1 is a block diagram schematically showing an arrangement of such a multiple parallel processor. A processor apparatus 20 comprises an integer processor 1 which chiefly controls data transfer from a memory and an execution flow, and one or more than one data processor 2 which chiefly carries out data processing defined by an extended instruction. The integer processor 1 chiefly carries out an addition/subtraction instruction, a branch instruction, a load instruction into a data memory, data read/write instructions, etc. On the other hand, the data processor 2 carries out data processing including, for example, an arithmetic operation defined by an extended instruction, such as an SIMD (Single Instruction stream Multiple Data stream), in parallel with the integer processor 1.
By operating the integer processor 1 and data processor 2 concurrently, two or more operation instructions can be carried out simultaneously in parallel in one clock cycle.
The instruction format that operates the processor apparatus 20 comprises, as shown in FIG. 2 for example, an instruction portion 71 that defines an operation of the integer processor 1, and another instruction portion 72 that defines an operation of the data processor 2. Each of these instructions 71 and 72 comprises a 32-bit instruction, for example.
However, the conventional multiple parallel processor apparatus 20 has the following problems. That is, an instruction string of a program to be carried out by the processor apparatus 20 includes a great number of instructions that define a single operation processing, by which the integer processor 1 alone is run even for an extended instruction. For an instruction format corresponding to such a single operation processing, the conventional processor apparatus 20 has to embed an instruction not to run any unit (no operation instruction: NOP instruction) into the portion 72 that defines an operation of the data processor 2 in the instruction format shown in FIG. 2. Consequently, utilization of instructions, especially extended instructions, is reduced, and a capacity of an instruction memory for storing instructions is undesirably increased.
The present invention is devised to solve the problems of the conventional multiple parallel processor, that is, an extended instruction is not utilized efficiently when carrying out a single operation, and a capacity of an instruction memory for storing instructions is undesirably increased.
It is therefore an object of the present invention to provide a multiple parallel processor capable of carrying out a plurality of operations in one clock cycle, which is a parallel processor capable of improving utilization of an extended instruction in a single operation mode by generating a control signal to stop the operation of any other data processor (coprocessor) and sending the control signal to the other data processor, and thereby improving availability of the instruction memory.
According to an aspect of the present invention, there is provided a parallel processor for processing a plurality of operation instructions in one cycle in parallel, comprising:
a first operation processor; and at least one second operation processor, the first operation processor including,
an operation mode retaining unit for retaining an operation mode indicating whether or not the second operation processor should be run in parallel to carry out an operation instruction, wherein the operation mode has a first mode in which the first operation processor alone is operated, and a second operation mode in which both of the first operation processor and the second operation processor are operated,
a control unit for, in case that the operation mode is the first operation mode, in accordance with the operation mode, supplying the first operation processor with an instruction sequence that defines an operation of the first operation processor, and for generating a control signal to halt an operation of the second operation processor and supplying the control signal to the second operation processor, whereby as to an instruction of the first operation mode, the second operation processor is not operated without embedding an instruction that defines an operation of the second operation processor in the instruction sequence retained in an instruction memory, and
an instruction execution unit for switching the operation mode in accordance with an input decoded instruction.
When the operation mode is the second operation mode, the control unit may supply the first operation processor with an instruction string that defines an operation thereof, and supply the second operation processor with an instruction string that defines an operation thereof.
The control signal may be a no operation instruction.
In the first operation mode, the instruction sequence retained in the instruction memory may include only an instruction that defines an operation of the first operation processor.
The control unit may include a no operation instruction retaining unit for retaining the no operation instruction; and in the first operation mode, the instruction string retained in the instruction memory may constantly include a plurality of instructions.
Alternatively, the control signal may be a signal that stops a supply of a clock to the second operation processor.
Alternatively, the control signal maybe a disable signal of the second operation processor.
The instruction execution unit may switch the operation mode retained in the operation mode retaining unit by executing a sub-routine call instruction directing an operation mode switching.
Here, the operation mode retaining unit may be an operation mode register; the control unit may include a first return address register for retaining a return address from the sub-routine call instruction; the instruction execution unit, when executing the sub-routine call instruction, may switch the operation mode by inverting a value in the operation mode register, and set information indicating inversion of the operation mode in the first return address register, and when returning from the sub-routine call instruction, may refer to the information indicating the inversion of the operation mode set in the first return address register, and if the inversion is set, return to the operation mode set before the sub-routine call instruction by inverting the value in the operation mode register.
The instruction execution unit may switch the operation mode retained in the operation mode retaining unit at an occurrence of an exception.
The operation mode retaining unit may be an operation mode register; the control unit may include a second return address register for retaining a return address from an exception program by which the exception is carried out; the instruction execution unit, at an occurrence of the exception, may switch the operation mode by inverting the value in the operation mode register, and set information indicating inversion of the operation mode in the second return address register, and when returning from the exception, may refer to the information indicating the inversion of the operation mode set in the second return address register, and if the inversion is set, return to the operation mode set before the exception by inverting the value in the operation mode register.
The instruction execution unit may switch the operation mode by inverting the value in the operation mode retaining unit in accordance with information indicating inversion of the operation mode contained in a part of a jump address defined in a jump instruction.
The second operation processor may comprise a plurality of coprocessors; and the control unit, in the first operation mode, may operate the first operation processor alone by stopping clocks to the plurality of coprocessors other than the first operation processor.
According to another aspect of the present invention, the above parallel processor further comprises:
an extended operation mode retaining unit for retaining an extended operation mode indicating which of the plurality of operation processors should be operated to carry out the operation instruction in parallel,
wherein, the control unit supplies the control signal to, in accordance with the extended operation mode, the second operation processor other than the second operation processor which is indicated by the extended operation mode.
According to still another aspect of the present invention, there can be provides a computer system equipped with a parallel processor for processing more than one operation instruction in one cycle, comprising: a first operation processor; at least one second operation processor; and a data memory,
the first operation processor including,
an operation mode retaining unit for retaining an operation mode indicating whether or not the second operation processor should be run in parallel to carry out an operation instruction, wherein the operation mode has a first operation mode in which the first operation processor alone is operated, and a second operation mode in which both of the first operation processor and the second operation processor are operated,
a control unit for, in case that the operation mode is the first operation mode, in accordance with the operation mode, supplying the first operation processor with an instruction sequence that defines an operation of the first operation processor, and for generating a control signal to halt an operation of the second operation processor and supplying the control signal to the second operation processor, whereby as to an instruction of the first operation mode, the second operation processor is not operated without embedding an instruction that defines an operation of the second operation processor in the instruction sequence retained in an instruction memory, and
an instruction execution unit for switching the operation mode in accordance with an input decoded instruction.